1. Field of the Invention
The present invention relates to a cache memory employed as a high-speed local memory of a micro-processor.
2. Description of the Related Art
FIG. 10 shows the constitution of a conventional cache memory, which is an example of an instruction cache memory of a direct map system to be used in an instruction fetch operation of a microprocessor. The configuration of FIG. 10 comprises an input address 1, an address latch 2 for storing therein a low-order portion of the input address, an input address low-order portion 3, an address latch low-order portion 4, a data address selector 5 for selecting between the input address low-order portion 3 and the address latch low-order portion 4, a tag field a 6a, a comparator 7 for comparing a high-order portion of the input address with an address read from the tag field a 6a, a data field 8, a valid flag field a 9a for storing therein a valid flag designating validity of data in the data field 8, a read flag 10 obtained from the valid flag field a 9a, an update bus 11 for transferring therethrough update data of the data field 8, a data selector 12 for selecting between data read from the tag field a 6a and data from the update bus 11, output data 13, a hit signal 14 created from a signal from the comparator 7 and the read flag 10, a memory read request signal 16 to be supplied at a miss occurrence to a memory at another hierarchical level (to be simply referred to as a memory hereinbelow), a memory read acknowledge signal 17 delivered from the memory in response to the memory read request signal 16, and control means 18 for outputting the memory read request signal 16 to the memory and for receiving the memory read acknowledge signal therefrom.
Next, a description will be given of the operation of the conventional cache memory example thus configured.
FIG. 11 is a signal timing chart in the prior art memory. Referring now to this chart, the operation will be described in the operation order (in the cycle number order of C0 to C3).